Modling a State Machine in VHDL ... with trouble memorizing variables

Sorry! I tried to translate the code for a better understanding. I resend it with the necessary corrections (and in fact the full code I'm working with). I attach also the simulation result (why does the accumulate signal - and so the output - go from 0 to 1 without control????):

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

use ieee.std_logic_unsigned.all;

entity Counter is

-- counts three ticks of the signal signal_to_monitor -or thats what I wish

-- the output signal is integer just to show the evolution in the waveform simulator

port(

clk: in std_logic;

reset,signal_to_monitor: in std_logic;

output: out integer

);

end Counter;

architecture Behavioral of Counter is

constant NUM_TICKS : integer := 3;

type possible_states is (first_st,second_st);

signal next_state,state: possible_states;

signal accumulate: integer range 0 to 2;

begin

RefreshState : process (clk,reset)

begin

if (reset='1') then

state <= first_st;

elsif (clk'event and clk='1') then

state <= next_state;

end if;

end process RefreshState;

process (state,signal_to_monitor)

begin

next_state <= state;

case state is

when first_st =>

-- no ticks yet

if (signal_to_monitor ='1') then

-- count one tick and go to the 'counting' state

accumulate<=accumulate+1;

next_state <= second_st;

else

accumulate <=0;

next_state <= first_st;

end if;

when second_st =>

-- if the signal goes to one again, count one more till you arrive to NUM_TICKS

-- then fall back to first_state

if (signal_to_monitor = '1') then

accumulate <=accumulate +1;

end if;

if (accumulate = NUM_TICKS) then

--

next_state<=first_st;

end if;

end case;

-- just to have a look at the waveform I generate the output here

output <= accumulate;

end process;

process (state)

begin

--do nothing as the output has been generated just for debugging purposes

end process ;

end Behavioral;