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Altera_Forum
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15 years ago

Modling a State Machine in VHDL ... with trouble memorizing variables

Hi, I'm trying to make a state-machine wich remains in one of the states until one of the variables goes from zero to one three times. I assume it should be quite simple, but after some days I ...
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Altera_Forum
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15 years ago

Your code is unreadable, because you're mixing original spanish and translated signal and state names. Please post either your original or another consistent code.