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Altera_Forum's avatar
Altera_Forum
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17 years ago

Modify IP-CORE Ssram

Hello, I'm trying to build a system in the SOPC-Builder with a Ssdram(Clock of whole system and components 100Mhz). The problem that I have is that running at 100 Mhz the IP-CORE of Ssram prod...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

Thanks for the answer so quickly.

I kwnow that ssram supports 100Mhz and more frequency. The problem is that I have made a system running at 50Mhz and it goes, when I change to 100 Mhz in the Nios II appears an error telling me:" Verify failed between adress 0xXXXXX and 0xXXXXX".

Then I reviewed the verilog code that SOPC Builder has made of the Ssram component and I doubt if the wait of read and write are well made, because the structure is a state machine which depends of the clock. So if the clock changes maby these times change. I don't kwnow enough of verilog so I'm a bit lost with the archive name.v and the other archive name.tcl that goes with the component, that's why I ask for help.

I think that this is the problem, but maby(sure) I'm wrong, if anybody can suggest more ideas.

P.D Sanmao: I have introduce the clock with the phase(-3ns) and the error continuos the same.

Thanks a lot.