Modelsim Help

I am learning modelsim and verilog

I have created a module and testbench but in simulation using the command:

vsim -novopt "testbench name"

I keep getting an initial high z input and don't care outputs.

Perhaps it is something in my code?

Original code:

module threeBitCounter ( counterValue, count, reset, clock);

input count; // Increment our counter on rising edge of 'count'

input reset; // Reset our counter on rising edge of 'reset'

input clock; // Synchronize outputs to clock

output reg [2:0] counterValue; // Internally store the counter value

// This takes care of synchronously driving the outputs

always @ ( posedge clock or negedge reset )

begin

if( reset == 1'b0 ) counterValue <= 3'b000;

else if( count ) counterValue <= counterValue + 1'b1;

else counterValue <= counterValue;

end

endmodule

TestBench code:

`timescale 1 ns / 1 ns

module threeBitCounter_testbench;

//define inputs/outputs

wire [2:0] cval;

reg reset;

reg clk;

reg countThisEvent;

threeBitCounter I1 ( cval, countThisEvent, reset, clock);

//set clock

always

# 10 clk = ~clk;

//Exercise the Counter

initial begin

reset = 1'b1; clk = 1'b0; countThisEvent = 1'b0;

# 4 reset = 1'b0;

# 4 reset = 1'b1;

# 7 countThisEvent = 1'b1;

# 20 countThisEvent = 1'b0;

# 20 countThisEvent = 1'b0;

# 20 countThisEvent = 1'b0;

# 20 countThisEvent = 1'b1;

# 20 countThisEvent = 1'b0;

# 20 countThisEvent = 1'b0;

# 20 countThisEvent = 1'b0;

end

endmodule