Modelsim Error: (vsim-3555) Identifier is not a unit name for the physical type

What library/package are you using to do this? You don't show that part of your code. A typical setup would be:

LIBRARY ieee;

USE STD.TEXTIO.ALL;

USE ieee.std_logic_1164.ALL;

USE ieee.std_logic_textio.ALL;

and I don't see that you've set up a file handle:

FILE vectorfile: TEXT OPEN READ_MODE IS "input_vectors.txt";

And if you're using TEXTIO, you don't need to read the spaces. They're skipped automatically.

Hi Naveen,

Typically, VHDL testbench would have a bone

1. Library,package used

2. Tb Entity declaration,

3. Testbench arcitecture

I only see the procedure to read input file, no UUT, component declaration and port mapping signal. You may find below link helpful creating VHDL Tb

https://www.nandland.com/vhdl/tutorials/tutorial-your-first-vhdl-program-part2.html

Some tutorial of testbench with reading file for value of input port.

https://www.nandland.com/vhdl/examples/example-file-io.html

Below link is full flow of creating project --> HDL file create --> Tb create (using Quartus template after you compile) --> simulation flows

http://denethor.wlu.ca/pc120/quartus_testbench.shtml#:~:text=You%20can%20get%20Quartus%20to,put%20statements%20for%20your%20simulation.

Generate TB using Modelsim (muc more easier)

https://www.youtube.com/watch?v=qZNL1C0TwY8

Thanks,

Regards