Occasional Contributor
Super ContributorHi Naveen,
Typically, VHDL testbench would have a bone
1. Library,package used
2. Tb Entity declaration,
3. Testbench arcitecture
I only see the procedure to read input file, no UUT, component declaration and port mapping signal. You may find below link helpful creating VHDL Tb
https://www.nandland.com/vhdl/tutorials/tutorial-your-first-vhdl-program-part2.html
Some tutorial of testbench with reading file for value of input port.
https://www.nandland.com/vhdl/examples/example-file-io.html
Below link is full flow of creating project --> HDL file create --> Tb create (using Quartus template after you compile) --> simulation flows
Generate TB using Modelsim (muc more easier)
https://www.youtube.com/watch?v=qZNL1C0TwY8
Thanks,
Regards
Occasional ContributorHello,
Sorry for not posting the complete testbench. I thought the logic implemented in the process would be sufficient to convey the information. The below attachment has the complete testbench.
Also, I found out that the error was due to not reading the first data (time value) from the text file in the right manner. After removing the time values from the text file, I could see that the simulation started and test vectors were assigned to the input ports. I have the below questions:
1. How do I read the real value data ex: 206.3, 209.8, 210.2 etc from a text file in my testbench?
2. How do I drive the bidirectional data bus in my testbench? I have tried this in line 151 of the attachment. Let me know if this is correct:
s_AD <= s_AD_temp when s_E = '1' else (others => 'Z');
Thank you very much in advance!
Occasional ContributorHello, a short Update:
I could find a way to read real values. Just created a real variable and multiplied it with 1 ns and assigned it to time variable.
For example:
variable a: time;
variable b: real;
read(<line_variable>, b);
a = b * 1 ns;
I am using the s_WRN and s_RDN signals being sent to DUT to decide read and write operation.
I wrote something like this outside the process:
s_AD <= s_AD_temp when s_WRN = '0' else
(others => 'Z') when s_RDN = '0' else
s_AD;
So, I am writing s_AD_temp to s_AD when S_WRN is enabled, driving s_AD to "Z" when the DUT has to perform write operation or else s_AD is same as it is.
