Modelsim: compiling into libraries

I think you might be getting a bit confused. In VHDL, you have packages, which are part of a library. The standard format is:

library lib;

use lib.package.all;

The libraries do not have to be in any specific directory. The libraries just contain compiled code. Any code can go wherever you want to put it. But inside a library, local bits can be referenced via work (rather than specifying the library name). This allows the whole library to reference itself while you are free to call it whatever you want.

So in modesim, the libaries are created with the vlib command:

vlib some_library;

Then to compile code into a specific library, you can specify which library is the work library for that file:

vcom some_file.vhd -work some_library_path

some_library should be the path of the working directory for some_library.

If you already have a completly compiled library, you can use vmap to add a library to your work directory:

vlib some_library

vmap some_library some_library_path

(some_library_path will usually end with /work, because locally the directory is /work)

So basically, the answer to the questions is:

1. The compilation of the files, but you can work locally in a library with the files in then use vmap from another directory.

2. See above (use the -work option on vcom)

3. you are confused. the work.lib_one.all has nothing to do with file paths. It is the libary paths of compiled code.

Thank u for your answer,

yes, i'm a little bit confused. :)

So if I want to write:

library work;

use work.lib_one.all;

how have I to map the library lib_one?

Have I to map it into work library?

lib_one is not a library, it is a package in the library "work".

all you have to do is run:

vcom lib_one.vhd (or wherever the file lib_one.vhd is)

and it will compile it into the work library.

Thank you very much.

Now I've another problem:

I've compiled a library into a folder with this command:

vcom -reportprogress 300 -work lib_one c:/component.vhd

Component.vhd contains this component:

package clock_sim_package is

component clock_sim

generic

(

constant freq : integer:=10000000;

constant duty : integer:=50

);

port

(

enable : in std_logic;

output : out std_logic

);

end component;

end clock_sim_package;

library ieee;

use ieee.std_logic_1164.all;

entity clock_sim is

generic

(

constant freq : integer:=10000000;

constant duty : integer:=50

);

port

(

enable : in std_logic;

output : out std_logic

);

end clock_sim;

architecture clock_sim_arch of clock_sim is

begin

mainprocess : process

constant rduty : real:=real(duty)/100.0;

constant tclkh : time:=1 sec*((1.0/real(freq))*rduty);

constant tclkl : time:=1 sec*((1.0/real(freq))*(1.0-rduty));

begin

if enable='1' then

output<='1';

wait for tclkh;

output<='0';

wait for tclkl;

else

wait until enable='1';

end if;

end process mainprocess;

end clock_sim_arch;

Into the top I instanciate the component (under architecture..begin):

the_clock : clock_sim

generic map

(

duty=>50,

freq=>clock_freq

)

port map

(

enable=>'1',

output=>clk

);

but when I try to compile the top, this is the answer:

** Error: Identifier "clock_sim" does not identify a component declaration.

What am I doing wrong?

have you created a lib_one library? have you done this in your top.vhd file?

library lib_one;

use lib_one.CLOCK_SIM_PACKAGE.all;

Very good...that was the problem...sorry, i'm a newer in VHDL and Modelsim :)

but now I've got another problem...the last one:

In one package, i've declared:

package log_package is

procedure log_write(level_i : in integer; from_i : in string; str_i : in string);

procedure log_write(level_i : in integer; from_i : in string; bus_command_i : in t_bus_command);

procedure log_write(level_i : in integer; from_i : in string; bus_result_i : in t_bus_result);

end log_package;

...

so three procedures with the same name, but different input parameters;

in my top I've written:

entity top is

...

end;

architecture arch_top of top is

...<signals>...

begin

...

myprocess : process

procedure writetestresult(test_name_i : in string; result_i : in boolean) is

begin

if result_i then

log_write(log_level_essential,instance_name,"passed " & test_name_i);

else

log_write(log_level_essential,instance_name,"failed " & test_name_i);

end if;

end procedure writetestresult;

begin

...

end process myprocess;

end arch_top;

Modelsim get me an error:

** Error: (vcom-1136) Unknown identifier "log_write".

Where am I going wrong?

have you included the log_package?

library wherever_log_package_is_lib;

use wherever_log_package_is_lib.log_package.all;

i've compiled it, and other files, using the command u told me earlier:

vcom C:/utils_package.vhd

vcom c:/log_package.vhd

vcom C:/bus_control_package.vhd

vcom C:/clock_sim_package.vhd

...

and in the top:

library work;

use work.log_package.all;

use work.clock_sim_package.all;

use work.reset_sim_package.all;

use work.utils_package.all;--

use work.serial_io_mux_package.all;

use work.serial_io_demux_package.all;