Model sim testbench

Question

Hello,

I have a test bench that simulate a 32bit data bus interfacing my fpga.

I would like my test bench to be able to inject data to fpga from a file.

so, testbench will read data from a file and transmit it to the fpga entity.

my code is in vhdl.

Does anybody know how to do that?

thanks

altera_forum · Answer

You cannot transmit data to the FPGA from the simulator. You will need to build a link for that, like via RS232

nless you're just trying to test your design in the simulator and do file IO for simulation purposes (not on real hardware)

altera_forum · Answer

I am just trying to test my design in the modelsim simulator.

I have this code in my test bench, the code increment data and drive it to my design.

while ( cnt_loop < 256 ) loop

data_sig <= data_sig + '1' ;

usb_data_out <=usb_data_out +'1';

wait for 10 ns;

cnt_loop := cnt_loop + 1;

Instead of increment data I would like this test bench to pull data from a file.

This way I can make any kind of file. its very comfortable.

Do you know how to do that?

altera_forum · Answer

you can use the std.textio library for file IO. it works very well with text files. There are plenty of tutorials on textio if you google it.

altera_forum · Answer

- do you have an example for std.textio commands?   read,write from a  file ?   - where sould I place this file?

altera_forum · Answer

http://lmgtfy.com/?q=textio+tutorial

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