model a buffer in VHDL

Hello Dt_Conan,

Is this model for synthesis or simulation?

If it is for sythesis, you cannot define a delay in terms of seconds, but cycles; and also, during those cycles you will have to keep the data registered, either using components (as in your code), or as Kaz has explainedAs Kaz has explained, by

"Your work is just registers and you can equally just infer them i.e. clocked process saying output <= input (clock itself should not be registered)."

If it is for simualtion purposes, than you can use a struct like

a <= b after 1ns; (VHDL)

Cheers.