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That does not make sense (at least to me). Why would you instantiate the Verilog top-module in your VHDL, as then its no longer the top-level module?!!
The key requirements for your top-level design are that its port names match the pin constraints. Had you created a top-level VHDL file with *exactly* the same port names as the Terasic example *AND* used the same pin assignments, then your top-level VHDL is identical to Terasic's. If you do not like their port names, then you can change them in your top-level VHDL *AND* in the pin assignments.
You can use the Pin Planner to view the pin assignments. You can export the project as a Tcl file to see those constraints.
Cheers,
Dave
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All of my code is in VHDL. The only thing that isn't is the Verilog module that has the board signal names. I did what you said and made a VHDL file with the board signal names and got rid of the Verilog. The goal is not to have to do that extra task.
I would like to keep the Verilog module as Terasic generates it and just use my VHDL file to instantiate it to get access to the signals.
As i pointed out, that doesn't work. The Verilog file is the Top-Level Entity. I even tried making the VHDL file the Top-Level Entity. Neither works.
Why not. The signals from the VHDL connect to the Verilog signals so it seems reasonable to me that the electrical connections are there.
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