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Altera_Forum
Honored Contributor
Honored ContributorMixing VHDL and Verilog
I have the Terasic Cyclone V board. They generate a Verilog top module with the board signal names that connect to the pins. I have a VHDL file that instantiates this Verilog top module to get acc...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- I have a VHDL file that instantiates this Verilog top module to get access to the board signals --- Quote End --- That does not make sense (at least to me). Why would you instantiate the Verilog top-module in your VHDL, as then its no longer the top-level module?!! The key requirements for your top-level design are that its port names match the pin constraints. Had you created a top-level VHDL file with *exactly* the same port names as the Terasic example *AND* used the same pin assignments, then your top-level VHDL is identical to Terasic's. If you do not like their port names, then you can change them in your top-level VHDL *AND* in the pin assignments. You can use the Pin Planner to view the pin assignments. You can export the project as a Tcl file to see those constraints. Cheers, Dave
