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Altera_Forum's avatar
Altera_Forum
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16 years ago

mixed 3.3V and 1.2V I/O interface

Hi,

This is probably simple to answer:

I am working with the CycloneIII, It is interfacing a microcontroller with 3.3V on one side, and also has interfaces of 1.2V digital devices.

I supply the I/O banks with 1.2V or 3.3V on its VCCIO pins to support the different interface voltage levels.

My question is : is that enough, or should i use the VREFB pins as well?

Thanks in advance'

Gabi

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    No that's all you have to do. Vref pins are only used for I/O standards that require a reference voltage for input. SSTL is one such example. DDR memory interfaces use the reference voltage.

    The real answer to your question lies in the Cyclone III handbook. See Table 6-4 on page 6-12 of the following document:

    http://www.altera.com/literature/hb/cyc3/cyc3_ciii5v1_02.pdf

    If it doesn't say "Voltage-referenced" in the Type column, you don't need a reference voltage. More details can be found in the Cylcone III datasheet:

    http://www.altera.com/literature/hb/cyc3/cyc3_ciii52001.pdf

    Jake
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    I've got it...Thank you!

    I will connect those VREFB pins to GND, is that okay ?

    Thanks in advance'

    Gabi
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    Here is the guidance from the Cyclone III pin connection guidelines:

    --- Quote Start ---

    Input reference voltage for each I/O bank. If a bank uses a voltage-

    referenced I/O standard for input operation, then these pins are used as the

    voltage-reference pins for the bank. If voltage reference I/O standards are

    not used in the bank, the VREF pins are available as user I/O pins.

    If VREF pins are not used, the designer should connect them to either the VCCIO

    of the I/O bank in which the pin resides or GND. Decoupling depends on the

    design decoupling requirements of the specific board. See Note 5. When VREF

    pins are used as I/O, they have higher capacitance than regular I/O pins which will

    slow the edge rates and affect I/O timing.

    --- Quote End ---

    If you are not going to use them as I/O pins, connect them to ground. However, make sure you don't accidentally configure them as I/O in your FPGA design and try to drive a logic high signal out on them.

    Jake