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Honored Contributor
Honored ContributorMissing output at node finder
HI guys.
My output node is missing when I tried to make functional simulation. Could somebody help me please. Only input port appear. Here is my coding. Is it related with coding? library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity counter4bit is port( Clock: in std_logic; Reset: in std_logic; Addr: out std_logic_vector(3 to 0)); end counter4bit; architecture Behavioral of counter4bit is signal count:std_logic_vector (3 downto 0); begin process(Clock,Reset,count) begin if Reset='1' then count <="0000"; elsif rising_edge (clock) then count <= count + '1'; end if; end process; Addr <= count; end Behavioral;2 Replies
Altera_ForumHi,
no idea what tool you're using, so let me start with the code. You declared the output as "3 to 0", which means "all the way from 3 up to 0". That's a negative range, and therefore a null range. You should make it "3 downto 0", as in the signal declaration. Also, it is unnecessary to put "count" into the process' sensitivity list. The process is synchronous, so when a signal changes, nothing happens until the next clock (or the next reset). Also, depending on your stimulus, the signal might become pruned if e.g. the reset is always '1' or the clock is static. As I said, no idea what tool you're using. ModelSim would AFAIK leave the signal there, in a static level. Best regards, GooGooCluster- Altera_Forum
Thanks GooGooCluster. I already fix it.
