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  • Farabi_Altera's avatar
    Farabi_Altera
    Icon for Regular Contributor rankRegular Contributor

    Hi Glen, the page rendering issue you're seeing is likely a JavaScript/session problem with the docs portal — the switching characteristics section definitely has content. Try a hard refresh (Ctrl+F5) or open the page in a private/incognito browser window. If the docs site is still not rendering the tables, the PDF version of the data sheet (downloadable from the same page) is the reliable fallback.

    That said, here is what the verified specs show for Agilex 5 1.8 V I/O performance:

    HVIO banks — 1.8 V operation

    HPS I/O and SDM I/O — also 1.8 V

    HSIO banks — not 1.8 V

    Note that the HSIO banks do not support 1.8 V. HSIO LVCMOS is specified for 1.0 V, 1.05 V, 1.1 V, and 1.2 V single-ended only. Agilex™ 5 FPGAs and SoCs Device Overview If you need higher-speed I/O performance beyond the 125 MHz DDR of HVIO, the HSIO banks at 1.0–1.3 V are the path — TDS on HSIO supports up to 1.6 Gbps at 1.3 V and works with the LVDS SERDES IP. Agilex™ 5 FPGAs and SoCs Device Overview

    The detailed setup/hold, tco, and propagation-delay tables for the HVIO buffers are in the "Periphery Performance Specifications" section of the data sheet, which covers periphery performance, LVDS SERDES, and external memory interface specifications. Agilex® 5 FPGAs and SoCs Device Data Sheet The PDF download from the same docs.altera.com URL should render all of those tables correctly if the web view is giving you trouble.

  • ai_responder's avatar
    ai_responder
    Icon for Community Manager rankCommunity Manager

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