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Altera_Forum
Honored Contributor
Honored Contributorminimum system clock required
Dears, I'm making a SPI interface in FPGA to interface with the SPI interface of a processor. The details as below: • SPI of processor will always act as master. Slave for FPGA. • SPI Clk: 25mhz...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- One more question, is there any metastability problem in my design? --- Quote End --- Should be O.K. by double registering of SCK and SS. --- Quote Start --- Could you show me more details? --- Quote End --- Domain crossing data transfer is easy for write data, register the data in the SCK domain, transfer the update event to the sysclock domain, e.g. by a toggle synchronizer. The data can be expected to be stable and consistent when the update event arrives. Read data transfer is more difficult. A suitable method depends on the amount of data (number of different read addresses). A straightforward way is to have registers permanently updated by the sysclock, update is paused while synchronized SS is active. If you have too many data, it can be fetched after the address is decoded, possibly needing a few empty SPI clock cycles between address and data phase.
