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Altera_Forum
Honored Contributor
Honored Contributorminimum system clock required
Dears, I'm making a SPI interface in FPGA to interface with the SPI interface of a processor. The details as below: • SPI of processor will always act as master. Slave for FPGA. • SPI Clk: 25mhz...
Altera_ForumHonored Contributor
Honored ContributorIf you allow for SPI signal skew, asymmetrical SPI clock and arbitrary clock phase, the system clock frequency probably can't be much lower. You'll find out by adding these real world effects to your testbench.
Alternatively you can run the SPI interface from SCK and perform domain crossing data transfer, e.g. using registers with handshake or DCFIFO. That's my usual choice for SPI clock frequencies in the multi 10 MHz range.
