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Altera_Forum's avatar
Altera_Forum
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8 years ago

Minimal Cost configuration - Cyclone IV

I am working on an upgrade to a product that has been in production for ten years now, using a Cyclone II device. The existing FPGA is sufficient to the task, except it is at "end of life" and they want to be able to produce this product for another 10 years.

So I have migrated the design to a Cyclone IV device : EP4CE15F17C6

The FPGA design include a NIOS II CPU, which is the only processor in the system. Space is tight and I am trying to get everything to fit in the same basic board layout.

Where I have just run into a road block is the configuration device. The product had been using a EPCS device but it has been labeled "Last Buy"

As I understand it, the FPGA will require 4 Mbits. The executable code for the NIOS II is also stored in the configuration device and requires another 2 Mbits. So an 8 Mbit device would be ideal.

Apparently, there is no longer any such device.

I figured the best bet would be to use a EPCQ device.

While there are technically parts as small as 16 Mbits, anything under 256 Mbits has a 14 to 16 week lead time! That doesn't inspire me with confidence that the part will be available for a number of years down the road.

I am aware of other manufacturers making serial proms that would be compatible with the "Active Serial" configuration mode, but it is essential that the serial prom can also be written by the NIOS II CPU for a "remote upgrade" and I believe that this wouldn't work with the alternative devices.

What I am having trouble understanding is why the configuration device is going to end up costing more than the FPGA itself! The old design had a FPGA + Configuration solution that cost about $40. It is looking like a new solution is going to cost over $100!

Am I missing something?

5 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    8 years ago

    I took your advice and tried a MAX 10 build.

    Using a Cyclone IV part I was able to fit the design in a EP4CE15F17C6 part, which is in a 256 pin package, 165 I/O pins. I actually had one entire bank of I/O left over.

    Using the MAX 10 family the restriction ended up being the number of I/O pins that would support the DDR2 memory. The smallest / cheapest device that would support a x16 DRAM appears to be the 10M16DCU324I7G

    I haven't been able to find an actual package drawing for this part yet but I believe it to be a 15mm x 15mm BGA with 0.8 pad spacing. So it is a higher pin count device in a smaller area.

    To use this device pushes the PCB layout into an entirely different arena. Now we are talking additional layers and micro-vias. That just blows the cost savings out the window.

    What I was really hoping for was some information on how to do a remote upgrade of the serial prom when using one of the configuration proms made by another company.
  • Altera_Forum's avatar
    Altera_Forum
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    8 years ago

    --- Quote Start ---

    I am aware of other manufacturers making serial proms that would be compatible with the "Active Serial" configuration mode, but it is essential that the serial prom can also be written by the NIOS II CPU for a "remote upgrade" and I believe that this wouldn't work with the alternative devices.

    --- Quote End ---

    If you can use something like an N25Q128A you shouldn't have to worry about the remote update as this uses standard SPI commands.

    The next option is to use such a device like the N25Q128A and put a small micro-controller between it and the FPGA?
  • Altera_Forum's avatar
    Altera_Forum
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    8 years ago

    It appears that the N25Q128A is being replaced by the MT25Q series.

    My question now is: Can I just hook one of these device up (pre-programmed, or programmed via some other means) and have the FPGA configure from it in the active serial mode?

    Or does it require putting down addition additional logic to feed the data in passive serial mode?