Migrating M9K design from Arria II to V, missing old-data functionality?

Good afternoon,

We have a design that implements a useful data structure (described below) in Arria II using two M9K blocks. However, in Arria V the design can not be implemented as it requires one of the memories to operate in true dual port mode with same-port read-old-data behaviour. In Arria V, between the two DIFFERENT ports you can have read-old-data behaviour, but it is no longer possible for a write through one of the ports to see the data it is overwriting. Is there a work-around or some way to emulate the old memory behaviour, possibly at an increased hardware cost?

The data structure we need is essentially a random-access collection of stacks. It supports these operations concurrently:

table.prepend(key, value)

table.get_and_clear(key)

... both of these operations can happen at the same time (to different keys).

The first operation adds "value" to a linked-list rooted at key. The second operation returns the head pointer of the linked list rooted at key and clears the head pointer.

We implemented this using two memories. One memory was for the "next" pointer of values and the other memory held the keyed head pointers.

The get_and_clear method executes a write of '0' to 'key', but due to the nature of M9Ks in Arria II, it gets the old head pointer at the same time for free. Thus, one of the ports of the true dual ported RAM can execute a read+clear to the 'key' address simultaneously.

The prepend(key, value) method executes a write of 'value' to 'key'. Again, due to the nature of M9Ks in Arria II, we get the old value of 'key' returned during this operation which we can then put into the "next" pointer in the other memory.

Essentially, we used the true dual ported M9K as a two-write two-read ported memory. This was possible because the read+write operations were always paired such that there were only two addresses, and each address executed a simultaneous read-old-data and write new data.

I know of techniques to implement two-write two-read ported memory in general, but they are very expensive. Our old approach cost us a single M9K block and allowed us to instantiate many copies of the core. Is there a clever way to exploit the fact that the 2R2W memory only uses two addresses to solve this problem more cheaply than the general case? It's quite a pity that the Arria V dropped this mode of operation.