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Unfortunately, this solution does not address the need for debugging via JTAG. I need to be able to use signal tap and the nios II EDS debugger.
I don't want to have to break out all of the FPGA JTAG pins to a connector.
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Unfortunately, without emulating a USB-Blaster exactly, you will not get the functionality you want.
You could probably get most of the functionality you want working via a custom USB interface, however, it may be more work than it is worth. You would still need to wire up the JTAG pins on the FPGA to your micro, and then implement the JTAG device protocols in your micro software. Given that you've got that wiring, you may as well include a JTAG header.
I've looked at the Virtual JTAG protocol, and that's pretty straightforward (though the simulation model is completely broken). You could use this to implement a JTAG-UART for processor interfacing (or reverse engineer the JTAG-side of the Altera JTAG-UART).
The NIOS debugger interface and the SignalTapII protocol would probably require reverse engineering (using SignalTapII to view the JTAG transactions).
Did you really want to go this route? It might be easier to add a JTAG header on your board for using when debugging, and then have your USB microcontroller and a UART interface to the FPGA for 'normal operation'. I think once you've got your FPGA programmed and your first 'Hello World' program running, you can do a lot of debugging via the normal serial interface over your micro's USB interface. Having to connect a USB-Blaster to debug the more difficult problems will be a lot less work than the reverse engineering of the JTAG protocols.
Cheers,
Dave
Honored Contributor
