--- Quote Start ---
This is a much simpler proposition then.
You just need to wire the FPGA configuration pins for passive serial, or fast passive parallel mode, and toggle the pins at the FPGA to program it appropriately. This is all described here for a VHDL implementation, but you'll get the picture:
http://www.ovro.caltech.edu/~dwh/carma_board/fpga_configuration.pdf (
http://www.ovro.caltech.edu/%7edwh/carma_board/fpga_configuration.pdf)
Cheers,
Dave
--- Quote End ---
Dave, thanks for the link. Lots of nice detail in there.
Unfortunately, this solution does not address the need for debugging via JTAG. It only addresses programming the FPGA.
I need to be able to use signal tap and the nios II EDS debugger.
I don't want to have to break out all of the FPGA JTAG pins to a connector.
That's why I'd prefer to use the USB on my micro.
Regards.
Honored Contributor
