Megawizard FIFO problem: Write and read request filling FIFO!

Hi,

Well this has to be the most bizarre problem I've ever encountered. I've found that the read request signal to the fifo occasionally results in the fifo used counter to be incremented and the data output corrupted. The fifo works normally for what i'd say to be several thousand read/write operations before the problem occurs.

I've implemented a megawizard fifo with the following specs:

Size: 64 words

Width: 32-bits

Read Clock: 133Mhz

Write Clock: 33.25Mhz (derived from read clock)

Clock sync: 2-stage clock synchronization (for asynchronous read and write clocks)

FIFO mode: Legacy

Memory: M4K

Optimised for: Speed

No overflow protection circuitry has been disabled.

I've attached a jpg of the signal tap capture and also a zip file containing the vector wavefile (VWF).

I'm using TimeQuest analyser and Quartus 7.2. Using the multicorner analysis TimeQuest does not report any timing violations.

I've defined the two clocks as the following in my SDC:

create_clock -name sclk -period 7.519 -waveform { 0.000 3.759 }  

create_generated_clock -name sclk_1_4 -source  -divide_by 4 

I chose the 2-stage synchronizer for the FIFO read/write operations as a precaution for any phase difference between the clocks that might cause a problem.

I can't think of anything else obvious. Any comments or suggestions would be appreciated.

Evan.