Megawizard FIFO problem: Write and read request filling FIFO!

Yeah, it was really bothering me, as I assumed the counters always counted up. Note that technically this isn't a metastability issue(where a register goes metastable), but a glitch(extra clock edge faster than the design will run at), causing the parity bit to get out of alignment with the count value. I was thinking it could be more robust without the parity value(and just do an XOR decode of the count value), which would make it always count up. This would make the design larger and slower, and the bottom line is that I've never seen a design that can handle clock glitches. So though the FIFO pointer might not count backwards, the counter would still jump to an incorrect value, state-machines would jump to bad states, etc. I often under-appreciate how dependent everything is on a good clock.