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Honored Contributor
Honored ContributorMegaWizard FIFO misses first write
I'm using a MegaWizard FIFO in my CPLD design and it always misses the first data written to it after a reset. I've done everything I could think of in changing the edge of the write signal, creating...
Altera_ForumHonored Contributor
Honored ContributorCan you please verify that your tx_read_fifo, tx_fifo_empty and tx_fifo_dat are clocked with clk. Furthermore, tx_byte, tx_wrreq and tx_fifo_full should be synchronous with tx_wrclk.
