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Altera_Forum
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15 years ago

Megawizard DDR signal primitive issue

Hopefully this is an easy one, but I have been hitting my head now for 2 days. This seems to be a low level primitive issue. These are my errors:

Error: Output port "OBAR" of PSEUDO_DIFF_OUT primitive "a2gx_ram_drive_build_wnios:a2gx_ram_drive_build_wnios_I|altmemddr_0:the_altmemddr_0|altmemddr_0_controller_phy:altmemddr_0_controller_phy_inst|altmemddr_0_phy:altmemddr_0_phy_inst|altmemddr_0_phy_alt_mem_phy:altmemddr_0_phy_alt_mem_phy_inst|altmemddr_0_phy_alt_mem_phy_dp_io:dpio|dqs_group[0].ddr2_with_dqsn_buf_gen.dqs_pdiff_out" must drive only one OBUF primitive on the I port and cannot drive anything else

Error: Input port IBAR of I/O input buffer "a2gx_ram_drive_build_wnios:a2gx_ram_drive_build_wnios_I|altmemddr_0:the_altmemddr_0|altmemddr_0_controller_phy:altmemddr_0_controller_phy_inst|altmemddr_0_phy:altmemddr_0_phy_inst|altmemddr_0_phy_alt_mem_phy:altmemddr_0_phy_alt_mem_phy_inst|altmemddr_0_phy_alt_mem_phy_dp_io:dpio|dqs_group[0].ddr2_with_dqsn_buf_gen.dqs_inpt_ibuf" must be driven by a top-level pin

Error: Output port DATAOUT of DDIO_OE primitive "a2gx_ram_drive_build_wnios:a2gx_ram_drive_build_wnios_I|altmemddr_0:the_altmemddr_0|altmemddr_0_controller_phy:altmemddr_0_controller_phy_inst|altmemddr_0_phy:altmemddr_0_phy_inst|altmemddr_0_phy_alt_mem_phy:altmemddr_0_phy_alt_mem_phy_inst|altmemddr_0_phy_alt_mem_phy_dp_io:dpio|altmemddr_0_phy_alt_mem_phy_dq_dqs:dqs_group[0].dq_dqs|dqsn_0_oe_ddio_oe_inst" must drive input port OE of I/O OBUF primitive or input port DATAIN of DELAY_CHAIN primitive

These signals are generated through the megawizard, utilizing the HPCII core. I get through 98% of synthesis and this comes up. Am I missing something here? My thoughts are that the problem is either in the qsf file or how I am hooking up the SOPC instantiation to my top-level.

5 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    did you run the pin_assignments.tcl? if not you might take a look at the User Guide to make sure you've followed all the necessary steps

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Info for those searching (in case anyone still is): I ran into this error when trying to port SIII ddr2 from 9.0 altmemphy up to 11.1 Qsys uniphy:

    Error (15853): Input port IBAR of I/O input buffer

    "stratixIII_3sl150_dev_niosII_standard_sopc:this_stratixIII_3sl150_dev_niosII_standard_sopc|

    stratixIII_3sl150_dev_niosII_standard_sopc_mem_if_ddr2_emif_0:mem_if_ddr2_emif_0|

    stratixIII_3sl150_dev_niosII_standard_sopc_mem_if_ddr2_emif_0_p0:p0|

    stratixIII_3sl150_dev_niosII_standard_sopc_mem_if_ddr2_emif_0_p0_memphy:umemphy|

    stratixIII_3sl150_dev_niosII_standard_sopc_mem_if_ddr2_emif_0_p0_new_io_pads:uio_pads|

    stratixIII_3sl150_dev_niosII_standard_sopc_mem_if_ddr2_emif_0_p0_altdqdqs:dq_ddio[0].ubidir_dq_dqs|

    altdq_dqs2_ddio_3reg_stratixiii:altdq_dqs2_inst|strobe_in"

    must be driven by a top-level pin

    Error (15852): Output port "OBAR" of PSEUDO_DIFF_OUT primitive

    "stratixIII_3sl150_dev_niosII_standard_sopc:this_stratixIII_3sl150_dev_niosII_standard_sopc|

    stratixIII_3sl150_dev_niosII_standard_sopc_mem_if_ddr2_emif_0:mem_if_ddr2_emif_0|

    stratixIII_3sl150_dev_niosII_standard_sopc_mem_if_ddr2_emif_0_p0:p0|

    stratixIII_3sl150_dev_niosII_standard_sopc_mem_if_ddr2_emif_0_p0_memphy:umemphy|

    stratixIII_3sl150_dev_niosII_standard_sopc_mem_if_ddr2_emif_0_p0_new_io_pads:uio_pads|

    stratixIII_3sl150_dev_niosII_standard_sopc_mem_if_ddr2_emif_0_p0_altdqdqs:dq_ddio[0].ubidir_dq_dqs|

    altdq_dqs2_ddio_3reg_stratixiii:altdq_dqs2_inst|pseudo_diffa_0"

    must drive only one OBUF primitive on the I port and cannot drive anything else

    It appears that Quartus II still generates has the original 9.0 assignment groups including ddr2_deva_dqs_n but now requires the _n side declaration “inout ddr2_deva_dqs_n” on the top level file stratixIII_3sl150_dev_niosII_standard.v as well:

    Adding this declaration to the top level stratixIII_3sl150_dev_niosII_standard.v resolves the error:

    inout ddr2_deva_dqs_p,

    inout ddr2_deva_dqs_n,

    The UniPhy also requires OCT RUP/RDN for each device which also need to be assigned.

    I ported for just ddr2_deva (device a) for now (pls check stratixIII_3sl150 dev kit web page for 11.1 installer update: standard design) but I assume making another UniPHY for device b will require the same adaptations (i hope). If I get bothe ddra & ddrb working together, I will update this thread.