Megawizard DDR signal primitive issue

Info for those searching (in case anyone still is): I ran into this error when trying to port SIII ddr2 from 9.0 altmemphy up to 11.1 Qsys uniphy:

Error (15853): Input port IBAR of I/O input buffer

"stratixIII_3sl150_dev_niosII_standard_sopc:this_stratixIII_3sl150_dev_niosII_standard_sopc|

stratixIII_3sl150_dev_niosII_standard_sopc_mem_if_ddr2_emif_0:mem_if_ddr2_emif_0|

stratixIII_3sl150_dev_niosII_standard_sopc_mem_if_ddr2_emif_0_p0:p0|

stratixIII_3sl150_dev_niosII_standard_sopc_mem_if_ddr2_emif_0_p0_memphy:umemphy|

stratixIII_3sl150_dev_niosII_standard_sopc_mem_if_ddr2_emif_0_p0_new_io_pads:uio_pads|

stratixIII_3sl150_dev_niosII_standard_sopc_mem_if_ddr2_emif_0_p0_altdqdqs:dq_ddio[0].ubidir_dq_dqs|

altdq_dqs2_ddio_3reg_stratixiii:altdq_dqs2_inst|strobe_in"

must be driven by a top-level pin

Error (15852): Output port "OBAR" of PSEUDO_DIFF_OUT primitive

"stratixIII_3sl150_dev_niosII_standard_sopc:this_stratixIII_3sl150_dev_niosII_standard_sopc|

stratixIII_3sl150_dev_niosII_standard_sopc_mem_if_ddr2_emif_0:mem_if_ddr2_emif_0|

stratixIII_3sl150_dev_niosII_standard_sopc_mem_if_ddr2_emif_0_p0:p0|

stratixIII_3sl150_dev_niosII_standard_sopc_mem_if_ddr2_emif_0_p0_memphy:umemphy|

stratixIII_3sl150_dev_niosII_standard_sopc_mem_if_ddr2_emif_0_p0_new_io_pads:uio_pads|

stratixIII_3sl150_dev_niosII_standard_sopc_mem_if_ddr2_emif_0_p0_altdqdqs:dq_ddio[0].ubidir_dq_dqs|

altdq_dqs2_ddio_3reg_stratixiii:altdq_dqs2_inst|pseudo_diffa_0"

must drive only one OBUF primitive on the I port and cannot drive anything else

It appears that Quartus II still generates has the original 9.0 assignment groups including ddr2_deva_dqs_n but now requires the _n side declaration “inout ddr2_deva_dqs_n” on the top level file stratixIII_3sl150_dev_niosII_standard.v as well:

Adding this declaration to the top level stratixIII_3sl150_dev_niosII_standard.v resolves the error:

inout ddr2_deva_dqs_p,

inout ddr2_deva_dqs_n,

The UniPhy also requires OCT RUP/RDN for each device which also need to be assigned.

I ported for just ddr2_deva (device a) for now (pls check stratixIII_3sl150 dev kit web page for 11.1 installer update: standard design) but I assume making another UniPHY for device b will require the same adaptations (i hope). If I get bothe ddra & ddrb working together, I will update this thread.