Forum Discussion
5 Replies
- AqidAyman_Altera
Regular Contributor
Hello,
Thank you for reaching out to Intel FPGA Community.
The fast model and slow model are subject to PVT (process, voltage, temperature) variations.
Regards,
Aqid Ayman
- phillip
New Contributor
Concept of PVT (process, voltage, temperature) variations are too abstract word for me.
Could you provide some example(diagram, graph, chart)?
- AqidAyman_Altera
Regular Contributor
Hi,
I found this one website from the external resource (out of Intel). Maybe the explanation there will be helpful for you to understand.
Please refer here: Process-Voltage-Temperature(PVT) Variation | vlsi4freshers
Regards,
Aqid Ayman
- phillip
New Contributor
Thanks for reply.
May i ask you one more think?
How could i decide one step input delay of IOE in given environment.
- AqidAyman_Altera
Regular Contributor
As we do not receive any response from you on the previous question/reply/answer that we have provided, please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.