Me and my simple questions: Can I do this in FPGA?

Hey I have found this library for fixed point operations “fixed_float_types.vhdl”, “fixed_generic_pkg.vhdl”, “fixed_generic_pkg-body.vhdl”,

and “fixed_pkg.vhdl”.

I might just declare values directly at binary in integer.decimal format and perform the operations normally with + and *

My question however if this kind of "libraries" are synthesizable and quartus II can work with them without problems. I know for example that the "/" division can be used in quartus II, but it won't synthesize in the FPGA, correct?

You dont need to consider binary at all - it doesnt matter what base the number is in - the equation is still the same. All computers, maths programs and everything work in binary - decimal is just a convenient representation for the human brain to understand. Just imagine your inputs are decimal. It will only make a difference for the number of bits required for operation.

If the input range is 0-99, then you need 7 integer bits (0-127). You cannot get exact resolution to make .999999, you need to decide how many fraction 2^n bits you need. 6 fractional bits gives you precision to the nearest 0.015625. 12 bits = 0.00048828125.

But usually you can work backwards - what precision is required at the output? this can give you the precision at the input.

http://www.alteraforum.com/forum/attachment.php?attachmentid=11659&stc=1

Sorry, I cant make it size smaller. (weird loading picture sys)

This is the equation more simplified. Exponents are only squares, no need of fractional squares. About ranges, Maximun integer number should be 99 (2 digits) and fractional part .999999 (6 digits), no negative numbers because subtraction is absolute value.

I will consider input and oupt binary so I can work more easily. I have been reading about fractional operations in VHDL, it seems that there are already a library for such, do you know about this?

--- Quote Start ---

Tricky now that you mentioned, I'm not that sure that the input should be decimal, but I'm quite sure that in the end I have to reflect somehow results in decimal (for showing purpose).

--- Quote End ---

If this is an image then is better to display as gray level or color shades than printing some number other than image is very limited on resolution.

--- Quote Start ---

Do you think doing divisions and multiplications of fractional values is any easy or feasible? My intention is to make this as simple as possible. Thanks so much!

--- Quote End ---

IQ mathematics are possible in FPGA logic as is possible on Integer processor without FP. ALso FP unit can be built on FPGA too..

Again the equation you posted has a lot of coefficients and indexes, if you wish some help please tell us about numbers and range.

Equation in first can be reworked using a negative exponent, this don't free from checking for negative values nor from division by zero. Exponent is fractional too so care must be applied to evaluate m coefficient can also raise to infinite values.

The board you own has a lot of power on both FPGA and HPS sections, both can handle that equation but for both you must have clean the scope.

From question you are posting I fear you need grasp VHDL before do this job is this right? If so some basic exercises can clean most of your doubt.

VHDL is a complex hardware descriptor language but also a programming and simulation language, it is not simple but not so difficult it just need some hint and patience and you can do everything you think in hardware/software.

Tricky now that you mentioned, I'm not that sure that the input should be decimal, but I'm quite sure that in the end I have to reflect somehow results in decimal (for showing purpose).

This is for a project in my course, I'm working with a hypothetical FPGA system that read a black and white picture in which every pixel has a different pixel intensity ranging from 0 to 99, those values are loaded into a list, that I have to cluster according to "Membership value" of every pixel into only 3 groups.

Each pixel should be processed by 1 PE to calculate "membership" as shown equation in my OP. (Then, each PE will communicate each other so they can "update" membership, but that's another story).

This equation includes Adding, subtraction, multiply and dividing. One big issue is that factional values (example: 0.0002) are generated in the process, (it also generates real periodic numbers like 0.1416.........., but I will keep them limited to a certain fixed number).

My work doesn't include how to catch the pixel intensity numbers, I will just take the values from a list, so I think you are right, maybe I can consider the list originally in binary, and in the end I cluster them in groups by binary also, without needing decimals ever.

Do you think doing divisions and multiplications of fractional values is any easy or feasible? My intention is to make this as simple as possible. Thanks so much!

--- Quote Start ---

Why do you want to use bcd? That makes things very complicated and use a lot of resources. Why not just work in binary like every other language? You can easily do arithmatic in vhdl with the IEEE.numeric_std library

A <= b + (c*d);

--- Quote End ---

Very interesting, so you suggest me to convert the input from decimal to entirely Binary, process everything inside and then to convert back to decimal?

Why do you want to use bcd? That makes things very complicated and use a lot of resources. Why not just work in binary like every other language? You can easily do arithmatic in vhdl with the IEEE.numeric_std library

A <= b + (c*d);

Hey rromano001, I have been doing an analysis. All what I say is from my ignorance, so you guys are free to correct me, First I must say that I won't be able to make this using the nice resources of my DE1 because my intention is to design a system that can handle not 2 or 3 PE but hundreds PE communicating each other in a torus network. Each of them have to be able to perform Adding, Subtraction, Multiply and Divide to perform the purposed Equation.

Regarding Floating Processing Unit I think is not necessary to make this kind of unit, Since I don't require so exact accuracy. Instead, I will use a very exact Fixed point method, making use of a group of registers to be filled with BCD numbers divided like this

88 . 88888888 (base-10) = 1000 1000 . 1000 1000 1000 1000 1000 1000 1000 1000 (Binary)

I'm pretty sure this would be enough, I did a couple of calculations with examples values and they never overpasses these limits and when they do, it doesn't matter for my purpose.

Input data can come directly in BCD directly or be converted from base-10, it doesn't matter.

Then I will construct the modules for each of operations, Adding, Subtraction, Multiply and Divide for separated. Something that I've found is that VHDL is a REALLY low language, I suspect I cannot directly operate two decimal numbers, but like in Assembler, I have to convert them to BCD and make operations of arithmetic adding, complements (for subtraction), carry, etc, in order to be able to Add decimals numbers. am I right??

Being honest, my professor seems not to have a single IDEA of what I'm doing, he is more of high level language, and he seems to think arithmetic operations is so simple as to start code and call it a day. :(

--- Quote Start ---

Thanks so much guys, I'll carefully study all your answers. My professor says I don't need to use Floating point unit for this, he says by designing a simple Adder-Multiplier-Accumulator would be enough (maybe is what Galfonz is mentioning). I will implement this on my FPGA but what i'm intending is to simulate a Chip which can perform this equation.

--- Quote End ---

Hi, Before to build a MAC unit you can found ready to use or make from scratch if this is your course goal, you need do some analysis of math underneath the equation you posted, so from where are coming Xi m Ci Cj and how long is summation and where data is stored? If you need retrieve from main memory then maybe really the DE1 Arm core can do better.

MAC unit is the base of DSP processing, better knowledge of data handling is a start point to evaluate faster and precise solution.

--- Quote Start ---

I have another question, this Floating Operation Module on the FPGA, Can it serves to several PE at the same time? Or it's a single module that will serve one PE one at a time? I ask this because I may need to do this equation in several PE at the same moment in paralell.

--- Quote End ---

To answer to this question is again necessary to know how indexes and parameter are handled, you can build a block and replicate on FPGA to compute more than one result as a SIMD or MIMD architecture but this need data get not overwritten from result, so:

where are to be stored uij results, from where are taken Xi Cj Ck m C, are same on input and output vector/matrix?