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Thanks so much guys, I'll carefully study all your answers. My professor says I don't need to use Floating point unit for this, he says by designing a simple Adder-Multiplier-Accumulator would be enough (maybe is what Galfonz is mentioning). I will implement this on my FPGA but what i'm intending is to simulate a Chip which can perform this equation.
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Hi, Before to build a MAC unit you can found ready to use or make from scratch if this is your course goal, you need do some analysis of math underneath the equation you posted, so from where are coming Xi m Ci Cj and how long is summation and where data is stored? If you need retrieve from main memory then maybe really the DE1 Arm core can do better.
MAC unit is the base of DSP processing, better knowledge of data handling is a start point to evaluate faster and precise solution.
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I have another question, this Floating Operation Module on the FPGA, Can it serves to several PE at the same time? Or it's a single module that will serve one PE one at a time? I ask this because I may need to do this equation in several PE at the same moment in paralell.
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To answer to this question is again necessary to know how indexes and parameter are handled, you can build a block and replicate on FPGA to compute more than one result as a SIMD or MIMD architecture but this need data get not overwritten from result, so:
where are to be stored uij results, from where are taken Xi Cj Ck m C, are same on input and output vector/matrix?
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