New Contributor
Regular ContributorHi
We have not hear from you and this Case is idling. It is not recommended to idle for too long.
Therefore following our support policy, I have to put this case in close status. My apologies if any inconvenience cause
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p/s: If any answer from the community or Altera Support is helpful, please feel free to give the best answer or rate 9/10 survey.
New ContributorHi Wincent :
Recently, I am on my travel vacation in Japan.
So, I Can't reply your message quickly.
thanks for your reply.
From your answer,
It seems that the agilex5 FPGA MIPI IO can not use alone (must use with Agilex5 MIPI D_Phy)
because "There is a block who handles the external incoming data deserialization
with its clocking for both HS and LP modes"
Is my understanding about this answer correct !?...
thank you~
