Honored ContributorDear Forum member:
I want to ask what means the error message "Internal Error: Sub-system: SUTIL, File: sutil_dump_max.cpp, Line: 4904". The Advanced Synthesis version is 1.01. Using device is EPM7160ELC84-*. Thanks. Toru.
Honored ContributorHi Toru,
Max+Plus II is ancient. You should update to use Quartus 11. If you have to build for FLEX10K, ACEX series devices, then use Quartus 9.0SP2. If you are using Windows 7, then I would recommend installing the older version of Quartus into a virtual machine running Windows XP (I haven't tried it under Windows 7). Cheers, DaveHonored ContributorDear Dave,
Thank you for your reply. --- Quote Start --- Max+Plus II is ancient. You should update to use Quartus 11. --- Quote End --- I understand that Max+Plus II is ancient. But Quartus does not support devices MAX7000(E), and I only have devices (EPM7032, EPM7128, EPM7160, etc), therefore, I just have to use Max+Plus II. So, please let me know anything about the error message. Regards, Toru.Honored ContributorThe error sounds like an internal bug
This bug wont be fixed by altera good luck finding a solution without an update.Honored ContributorDear Tricky,
Thank you for your reply. I will try to check any more. Regards, Toru.Honored ContributorHi Toru,
--- Quote Start --- But Quartus does not support devices MAX7000(E), and I only have devices (EPM7032, EPM7128, EPM7160, etc), therefore, I just have to use Max+Plus II. --- Quote End --- I just checked Quartus 9.0SP2 and it supports MAX7000AE, MAX7000B, and MAX7000S, so it looks like you are right, there is no MAX7000(E) support. --- Quote Start --- So, please let me know anything about the error message. --- Quote End --- There is no hope in getting help with an error message without seeing code, and even then, the error indicates a problem internal to MAX+Plus II. However, if the error is being caused by invalid syntax, you could try compiling your code with a newer version of Quartus (targeting a newer MAX7000 device), or with the Modelsim simulator, and then once you are convinced the code (and synthesized logic) is correct, go back to target the MAX7000E in MAX+Plus II. Cheers, DaveHonored ContributorDear Dave,
Thank you for your re-reply. --- Quote Start --- There is no hope in getting help with an error message without seeing code, and even then, the error indicates a problem internal to MAX+Plus II. --- Quote End --- Here is the code which is a decimal counter and a 7-segment-LED-display by verilog-HDL. Using crystal oscillator is 27MHz. When negative pulse received, 7-segment-LED displays received time(s).module dsk_counter3(CLK, PS1, PS2, FAN, RESET, SEG7_OE_B, SEG7);
input CLK, PS1, PS2, FAN, RESET;
output SEG7_OE_B;
output reg SEG7;
reg count_2ms;
reg cnt_2ms;
wire pulse_2ms;
reg PS1_cnt;
reg PS2_cnt;
reg FAN_cnt;
reg seg_PS1;
reg seg_PS2;
reg seg_FAN;
reg SEG_OE_cnt;
wire SEG_OE_digit;
reg SEGEN_O;
always @(posedge CLK or negedge RESET)
begin
if(!RESET)
begin
cnt_2ms <= 1'b0;
count_2ms <= 16'h0;
end else
begin
if(count_2ms == 16'hD2F0) // (27MHz / 1000 * 2 = 2ms(54,000count))
begin
cnt_2ms <= 1'b1;
count_2ms <= 16'h0;
end else
begin
cnt_2ms <= 1'b0;
count_2ms <= count_2ms + 16'h1;
end
end
end
assign pulse_2ms = cnt_2ms;
always @(posedge CLK or negedge RESET)
begin
if(!RESET)
begin
PS1_cnt <= 4'b0000;
PS2_cnt <= 4'b0000;
FAN_cnt <= 4'b0000;
end else
begin
if(pulse_2ms == 1'b1)
begin
if(!PS1)
begin
if(PS1_cnt == 4'b1010) PS1_cnt <= 4'b0000;
PS1_cnt <= PS1_cnt + 4'b1;
end else if(!PS2)
begin
if(PS2_cnt == 4'b1010) PS2_cnt <= 4'b0000;
PS2_cnt <= PS2_cnt + 4'b1;
end else if(!FAN)
begin
if(FAN_cnt == 4'b1010) FAN_cnt <= 4'b0000;
FAN_cnt <= FAN_cnt + 4'b1;
end
end
end
end
always @*
begin
case(PS1_cnt)
4'b0000 : seg_PS1 <= 8'b00001010; // A-F-E-D-DotPoint-C-G-B
4'b0001 : seg_PS1 <= 8'b11111010;
4'b0010 : seg_PS1 <= 8'b01001100;
4'b0011 : seg_PS1 <= 8'b01101000;
4'b0100 : seg_PS1 <= 8'b10111000;
4'b0101 : seg_PS1 <= 8'b00101001;
4'b0110 : seg_PS1 <= 8'b00001001;
4'b0111 : seg_PS1 <= 8'b00111010;
4'b1000 : seg_PS1 <= 8'b00001000;
4'b1001 : seg_PS1 <= 8'b00101000;
default : seg_PS1 <= 8'b11111111;
endcase
case(PS2_cnt)
4'b0000 : seg_PS2 <= 8'b00001010; // A-F-E-D-DotPoint-C-G-B
4'b0001 : seg_PS2 <= 8'b11111010;
4'b0010 : seg_PS2 <= 8'b01001100;
4'b0011 : seg_PS2 <= 8'b01101000;
4'b0100 : seg_PS2 <= 8'b10111000;
4'b0101 : seg_PS2 <= 8'b00101001;
4'b0110 : seg_PS2 <= 8'b00001001;
4'b0111 : seg_PS2 <= 8'b00111010;
4'b1000 : seg_PS2 <= 8'b00001000;
4'b1001 : seg_PS2 <= 8'b00101000;
default : seg_PS2 <= 8'b11111111;
endcase
case(FAN_cnt)
4'b0000 : seg_FAN <= 8'b00001010; // A-F-E-D-DotPoint-C-G-B
4'b0001 : seg_FAN <= 8'b11111010;
4'b0010 : seg_FAN <= 8'b01001100;
4'b0011 : seg_FAN <= 8'b01101000;
4'b0100 : seg_FAN <= 8'b10111000;
4'b0101 : seg_FAN <= 8'b00101001;
4'b0110 : seg_FAN <= 8'b00001001;
4'b0111 : seg_FAN <= 8'b00111010;
4'b1000 : seg_FAN <= 8'b00001000;
4'b1001 : seg_FAN <= 8'b00101000;
default : seg_FAN <= 8'b11111111;
endcase
end
always @(posedge CLK)
begin
SEG_OE_cnt <= SEG_OE_cnt + 32'b1;
end
assign SEG_OE_digit = SEG_OE_cnt;
always @(posedge CLK)
begin
case(SEG_OE_digit)
2'b00 : SEG7 <= seg_PS1;
2'b01 : SEG7 <= seg_PS2;
2'b10 : SEG7 <= seg_FAN;
default : SEG7 <= 8'b11111111;
endcase
end
always @(posedge CLK)
begin
case(SEG_OE_digit)
2'b00 : SEGEN_O <= 3'b110;
2'b01 : SEGEN_O <= 3'b101;
2'b10 : SEGEN_O <= 3'b011;
default : SEGEN_O <= 3'b111;
endcase
end
assign SEG7_OE_B = SEGEN_O;
endmoduleThe code compiles correctly in Quartus. I don't see a problem, that can be expected to cause problems in max+plus2.
Apart from this point, som design details seems questionable in the code: - why are counting input events mutual exlusive (using else if). - do you intend to count 0 to 10, as the code does, or 0 to 9? - do you want to count negative edges or sample low state? - assuming the inputs are unrelated to CLK, synchronizing would be required to avoid wrong counting
