max+plus2 advanced synthesis error message

Dear Dave,

Thank you for your re-reply.

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There is no hope in getting help with an error message without seeing code, and even then, the error indicates a problem internal to MAX+Plus II.

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Here is the code which is a decimal counter and a 7-segment-LED-display by verilog-HDL.

Using crystal oscillator is 27MHz.

When negative pulse received, 7-segment-LED displays received time(s).

module dsk_counter3(CLK, PS1, PS2, FAN, RESET, SEG7_OE_B, SEG7);
	input CLK, PS1, PS2, FAN, RESET;
	output  SEG7_OE_B;
	output reg  SEG7;
	
	reg  count_2ms;
	reg cnt_2ms;
	wire pulse_2ms;
	
	reg  PS1_cnt;
	reg  PS2_cnt;
	reg  FAN_cnt;
	
	reg  seg_PS1;
	reg  seg_PS2;
	reg  seg_FAN;
	
	reg  SEG_OE_cnt;
	wire  SEG_OE_digit;
	reg  SEGEN_O;
	
	always @(posedge CLK or negedge RESET)
	begin
		if(!RESET)
		begin
			cnt_2ms <= 1'b0;
			count_2ms <= 16'h0;
		end else
		begin
			if(count_2ms == 16'hD2F0)		// (27MHz / 1000 * 2 = 2ms(54,000count))
			begin
				cnt_2ms <= 1'b1;
				count_2ms <= 16'h0;
			end else
			begin
				cnt_2ms <= 1'b0;
				count_2ms <= count_2ms + 16'h1;
			end
		end
	end
	
	assign pulse_2ms = cnt_2ms;
	
	always @(posedge CLK or negedge RESET)
	begin
		if(!RESET)
		begin
			PS1_cnt <= 4'b0000;
			PS2_cnt <= 4'b0000;
			FAN_cnt <= 4'b0000;
 		end else
		begin
			if(pulse_2ms == 1'b1)
			begin
				if(!PS1)
				begin
					if(PS1_cnt == 4'b1010) PS1_cnt <= 4'b0000;
					PS1_cnt <= PS1_cnt + 4'b1;
				end else if(!PS2)
				begin
					if(PS2_cnt == 4'b1010) PS2_cnt <= 4'b0000;
					PS2_cnt <= PS2_cnt + 4'b1;
				end else if(!FAN)
				begin
					if(FAN_cnt == 4'b1010) FAN_cnt <= 4'b0000;
					FAN_cnt <= FAN_cnt + 4'b1;
				end
			end
		end
	end
	
	always @*
	begin
		case(PS1_cnt)
			4'b0000 : seg_PS1 <= 8'b00001010; // A-F-E-D-DotPoint-C-G-B
			4'b0001 : seg_PS1 <= 8'b11111010;
			4'b0010 : seg_PS1 <= 8'b01001100;
			4'b0011 : seg_PS1 <= 8'b01101000;
			4'b0100 : seg_PS1 <= 8'b10111000;
			4'b0101 : seg_PS1 <= 8'b00101001;
			4'b0110 : seg_PS1 <= 8'b00001001;
			4'b0111 : seg_PS1 <= 8'b00111010;
			4'b1000 : seg_PS1 <= 8'b00001000;
			4'b1001 : seg_PS1 <= 8'b00101000;
			default : seg_PS1 <= 8'b11111111;
		endcase
		
		case(PS2_cnt)
			4'b0000 : seg_PS2 <= 8'b00001010; // A-F-E-D-DotPoint-C-G-B
			4'b0001 : seg_PS2 <= 8'b11111010;
			4'b0010 : seg_PS2 <= 8'b01001100;
			4'b0011 : seg_PS2 <= 8'b01101000;
			4'b0100 : seg_PS2 <= 8'b10111000;
			4'b0101 : seg_PS2 <= 8'b00101001;
			4'b0110 : seg_PS2 <= 8'b00001001;
			4'b0111 : seg_PS2 <= 8'b00111010;
			4'b1000 : seg_PS2 <= 8'b00001000;
			4'b1001 : seg_PS2 <= 8'b00101000;
			default : seg_PS2 <= 8'b11111111;
		endcase
		
		case(FAN_cnt)
			4'b0000 : seg_FAN <= 8'b00001010; // A-F-E-D-DotPoint-C-G-B
			4'b0001 : seg_FAN <= 8'b11111010;
			4'b0010 : seg_FAN <= 8'b01001100;
			4'b0011 : seg_FAN <= 8'b01101000;
			4'b0100 : seg_FAN <= 8'b10111000;
			4'b0101 : seg_FAN <= 8'b00101001;
			4'b0110 : seg_FAN <= 8'b00001001;
			4'b0111 : seg_FAN <= 8'b00111010;
			4'b1000 : seg_FAN <= 8'b00001000;
			4'b1001 : seg_FAN <= 8'b00101000;
			default : seg_FAN <= 8'b11111111;
		endcase
	end
	
	always @(posedge CLK)
	begin
		SEG_OE_cnt <= SEG_OE_cnt + 32'b1;
	end
	
	assign SEG_OE_digit = SEG_OE_cnt;
	
	always @(posedge CLK)
	begin
		case(SEG_OE_digit)
			2'b00 : SEG7 <= seg_PS1;
			2'b01 : SEG7 <= seg_PS2;
			2'b10 : SEG7 <= seg_FAN;
			default : SEG7 <= 8'b11111111;
		endcase
	end
	
	always @(posedge CLK)
	begin
		case(SEG_OE_digit)
			2'b00 : SEGEN_O <= 3'b110;
			2'b01 : SEGEN_O <= 3'b101;
			2'b10 : SEGEN_O <= 3'b011;
			default : SEGEN_O <= 3'b111;
		endcase
	end
	
	assign SEG7_OE_B = SEGEN_O;
	
endmodule

I do not try to synthesize this code by other tools yet.

I will be back after I found anything.

Regards,

Toru.