Maximum number of devices in JTAG chain with USB Blaster

The USB Blaster is working at a fixed 6 MHz TCK. It's using a shift register in the CPLD that is not providing programmable frequencies. In principle, it would be possible to modify the CPLD design. Also changing the crystal should basically work. But it's not neccessary for your purpose I think. There's no TDI/TDO delay chain issue, because the timing is regenerated at each chain device by a DFF, shifting the data one clock cycle.

The only problem is TCK and TMS fanout, which can be easily overcome by buffering. You should however care for correct source side series termination of TCK. The JTAG circuitry of FPGAs has fast logic elements, they can detect ringing TCK edges as double clocking.

The 6 MHz TCK JTAG chain has room for several 10 ns of additional delay. If the TCK to TDO delay at the USB blaster exceeds 1/2 TCK cycle, it fails however.

P.S.: In addition, there's a maximum length of chained IDCODE registers accepted by the Quartus Programmer when initially identifying the chain. But I have in mind a size of at least 512 bits, may be 2 or 4 times more. It should be documented somewhere.