MAX7000 power and Slew rate control

Hi FvM,

You are correct, there was a bug in my Verilog, I am still new to this languge. If you can point out what I am doing wrong in this example I will be grateful.

Clock was running at 24MHz. The intenet of the design is hopefully quite obvious.

Thanks,

Mark

=============

// Use I/Q shaft encoder input to

// control a 16 bit up/down counter

// use all available input edges

module IQ_interface(clk, I, Q, count);

output count;

input clk, I, Q;

reg last_I, last_Q;

reg [15:0]count;

always @(posedge clk)

begin

if(last_I != I) // detect change of I input

begin

last_I <= I;

if(I ^ Q) count <= count + 1; // incrementing appears to work OK

else count <= count - 1;

end

if(last_Q != Q) // detect change of Q input

begin

last_Q <= Q;

if(I ^ Q) count <= count - 1; // decrementing has the bug

else count <= count + 1;

end

end

endmodule