Altera_Forum
Honored Contributor
12 years agomax3000 GCLK, GCLR, OE pins use
Hi,
what one should do in Quartus II for global signals GCLK, GCLR and OE proper organization? For example, a Schematic File for MAX3000 design contains LPM_COUNTER with 'clock', 'clk_en' (clock enable) and 'aclr' (async Clr) Inputs and 'cout' (carry-out) Output which are correspondently connected to Input and Output pins of the Schematic File: <clk>, <eclk>, <clr>, <out> For GCLK1 signal (to make it really global clock): is it sufficient - to place <clk> input pin, - to connect it to the 'clock' pin of the LPM_COUNTER, - to assign the <clk> input to the Global Clock pin in the Pin Planner, - in 'More Analysis & Synthesis Settings' the 'Auto Global Clolck' option set On? For GCLR signal (to make it really global clear): is it sufficient - to place <clr> input pin, - to connect it to the 'aclr' pin of the LPM_COUNTER, - to assign the clr input to the Global Clear pin in the Pin Planner? And how the Global OE signal should be used to provide tri-state output on pin <out>, which is connected to 'cout' LPM_COUNTER pin? Should be - OE pin placed and assigned in Pin Planner to Global OE pin - tri-state primitives be placed for each output and controlled by the Global OE signal?