Honored ContributorHi
How would I create a bi-directional pin with open-collector output on a MAX3000 CPLD? I have started the design with an open collector driver driving the pin and a 541 type buffer for the input. The pin is externally pulled to 5V. VCC IO is 3.3V Will this work? Thanks Andre
Honored ContributorI assume you're referring to MAX3000A devices? You're doing it correctly. Though I'm not sure what you mean by 541 type buffer on the input (I assume you're referring to a 74xx541 part). Info is found on pages 20 & 21 of the datasheet:
http://www.altera.com/literature/ds/m3000a.pdf JakeHonored ContributorThanks for the reply,
Yes, MAX3000A and yes, 74xx541. I had previously read this part of the datasheet. This information is not really what concerns me as it meets all my requirements. It's the gates inside the device and the way in which they operate on the specified pin that concerns me. For this to work the "pin" must really just be a wire so that the open-collector drivers can pull the "pin" down and the 74xx541 buffer simply "see and transfer" the "pin" level. So on my schematic I have a 74xx573 (latch) followed by open collector drivers connected to the pin. On the pin I also have the 74xx541 so that I can read back the output state. My question is really how do I define the pin structure? (Did I mention that I am new at this) Thanks AndreHonored ContributorCan you attach a picture of your schematic?
JakeHonored ContributorHi
Here is the entire schematic in a Word doc. You can zoom in to get a better view. The (16) MOTORx_ENABLE_DIAG_A and MOTORx_ENABLE_DIAG_B pins need to be bi-directional. These are the pins that I am concerned about. All outputs are open collector (I see I need to add some more open collector buffers) note that I don't drive the CPLD with any type of clock. This is simple logic replacement and a lot of level shifting. The one CPLD replaces about 15-20 individual devices. The design just fits a epm3064A with 66 IO Thanks AndreHonored ContributorIt's basically correct. If Quartus doesn't accept the parallel connection of open drain driver and input to the bidirectional pin (it generally works in HDL entry), you can place bidir instead of open drain IO elements.
Honored ContributorHi Andre,
Did you have success with this implementation? I too am trying to interface with a 541, open-drain, but Quartus will not configure the 3064 in be open drain for some reason, thus the output pins are still driving 3.3v. Thanks!Honored ContributorHi
My application is working. I must be honest and say that I am not 100% sure that I have done everything correctly as this is the first time that I am using a modern CPLD. Did you look at my schematic? I have since made some minor changes. The 541 is really an input buffer. If you are using it as an output then simply replace it with 8 single open collector gates. I used the 74374 to latch data and then added 8 open collector gates with the IO pins set to BI-DIR. I have a 10K pull-up to 5V. Also if you are using my schematic then the 74138 select lines that drive the 74374 CLOCK need to be inverted again. Let me know if this helps. AndreHonored ContributorI was mostly interested in trying to get the 3064 to be configured as open drain, which was answered in another thread. I'll try it later tonight. Thanks for your help!
Honored ContributorWhy don't working this schematic into EPM3064A?
This is bus-arbitre for Z80A CPU (BUS is 5V).Honored ContributorWhy don't working this schematic?
MAX3000A (EPM3032A, EPM3064A). Lines of both buses is pulluped by 10K resistors.
.jpg){kind=link}
.jpg){kind=link}