MAX10:UFM Parallel Read Timing Details

I have verified the behavior of the read from the UFM in simulation.

According to the timing diagram in the user guide, the readdatavalid pulse is output 5 clocks after the read pulse in the 10M04/08/16/40.

However, when I ran the simulation on the 10M02, to my surprise, the readdatavalid pulse came out 58 clocks after the read pulse input. This is very slow. Does it still take 58 clocks in the actual device?

Hi ken_51,

Sorry for the delay. I'm checking this with the internal team and will get back to you with clarification.

Thanks for your patience.

Regards,

Fakhrul

Hi ken_51,

After re-checking the document, I realized that I may have overlooked something earlier. It is indeed expected behavior due to the significant gap between the maximum frequency for all devices in parallel mode, which is 116 MHz, and the 10M02 device, which only supports up to 7.25 MHz. This aligns with what FvM mentioned above.

Regards,

Fakhrul

Thank you very much.

I already understood that the maximum clock is 7.25 MHz.

However, I did not expect that it would take more than 50 clocks to send back the readdatavalid pulse.

There seems to be no effective solution to this problem.

I am giving up on the 10M02 device and replacing it with a larger capacity device.

Are you still checking in simulation or with real FPGA?

We gave up on 10M02 completely and replaced it with 10M08, which uses BlockRAM instead of UFM.

Hi ken_51,

Unfortunately, we also don't have a 10M02 to test on our end. However, based on its specifications, this is expected behavior.

Regards,

Fakhrul

As we do not receive any response from you to the previous notification that we provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.