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Altera_Forum
Honored Contributor
8 years agoIn the meantime, I have solved the problem by myself.
It was related to the PINs DRAM_UDQM and DRAM_LDQM. These pins have always been incorrectly created / designated (in version Quartus 16.1) in a Qsys "Generate HDL ..." I changed it as follows: # DRAM_LDQM,Unknown,PIN_V22,5,B5_N0,3.3-V LVTTL,,4ma,,, # DRAM_UDQM,Unknown,PIN_J21,6,B6_N0,3.3-V LVTTL,,4ma,,, DRAM_dqm[1],Unknown,PIN_V22,5,B5_N0,3.3-V LVTTL,,4ma,,, DRAM_dqm[0],Unknown,PIN_J21,6,B6_N0,3.3-V LVTTL,,4ma,,,