[MAX10] some I/Oport driven Low when Jtag Programming

Hi,

I use MAX10 [10M16SCU324C8G　supply3.3V] FPGA in our design.

While writing .pof, some user I/Opin is driven low. (ISP-CLAMP is disabled. USB-Blaster Rev.c is used.)

The user I/Opin (input setting pin) is connected to an external 3.3V buffer output (buffer is High output during writing). Therefore, a large current flows.

(1)

I/Opin is written as Tri-state in Configuration User Guide.

I interpreted that I/Opin was in Hiz state while .pof writing.(Is this wrong?)

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/max-10/ug_m10_config.pdf

--- Quote Start ---

2.1.2.3.1. ISP Clamp

When a normal ISP operation begins, all I/O pins are tri-stated.

--- Quote End ---

(2)

I have found the following articles that are expected to be similar. (10M 04 SCU324C8G)

https://www.intel.com/content/altera-www/global/en_us/index/support/support-resources/knowledge-base/component/2019/why-are-some--i-o-pins-status-of-10m04sau324i7g-device--low-rath.html

Since I designed with the Qurtus18.1 Lite, I generated and tried .pof with both the Quartus19.1 standard-edition and Lite-edition, but it was the same.

Is this a bug of Qurtus and 10M16SCU324C8G is not fixed?

(3)

To avoid this problem, I created .ips with [ISP CLAMP state editor] of Qurtus 18.1 programmer, enabled ISP CLAMP and wrote .pof.

For some reason, just changing one of the low driven pins to the high setting caused all the low driven pins to enter the weak pull-up state.

(Pin set to High is High output. All other user I/Opins are set to Tri-state.)

Is this a bug?

Also, it takes 6 minutes to write .pof with ISP CLAMP enabled.

(If it is invalid, it will end in about 10 seconds.)

Is it the specification that takes time?

Best regards.