MAX10 RSU

NIOS is NOT required for RSU implementation on MAX10s. You mislead people to the already known topics or examples. I struggled so much at RSU implementation with only fpga logic and it finally I made it. Intel's documentation about it just a couple of lines and it is awful.

For RSU implementation on fpga side you must have to 2 basic IPs: On-Chip Flash IP core (user guide: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/max-10/ug_m10_ufm.pdf) and Dual Configuration IP core (user guide: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/max-10/ug_m10_config.pdf).

The flash memory of max 10 splits into parts relative to your configuration mode. When applying RSU you have to select "dual compressed image". If you do that flash memory splits into 3 section that are CFM0, CFM1 and UFM. You must choose read-write in IP's settings for RSU. CFMs stand as "Configuration Flash Memory" and they holds the fpga's configuration image. UFM stand as "User Flash Memory" and it holds user memory if there any. All of that flash memories logically high when they are empty and you can't change low bit to high, you can just change high bit to low. So if you wanna rewrite this sections you must clear them before write.

After you write the rpd to the relevant CFM section with flash ip core you can set the dual config ip's config sel, config sel overwrite and reconfig settings and your fpga reboots from your upfated program. For this logic you can refer to: (https://community.intel.com/t5/Programmable-Devices/Discrete-RSU-User-Logic/m-p/1269878/highlight/true#M79509)