Honored Contributor
Honored ContributorI have a 50MHz clock coming into the FPGA: CLOCK_50
This signal routes to the internal pll input. The internal Pll generates 2 clocks, 50MHz and 80MHz. The flash and dual config modules run off the 80MHz clock. I have the following constraints in my sdc file: create_clock -name {CLOCK_50} -period 20.000 -waveform { 0.000 10.000 } [get_ports {CLOCK_50}] set_clock_uncertainty -rise_from [get_clocks {CLOCK_50}] -rise_to [get_clocks {CLOCK_50}] 0.020 set_clock_uncertainty -rise_from [get_clocks {CLOCK_50}] -fall_to [get_clocks {CLOCK_50}] 0.020 set_clock_uncertainty -fall_from [get_clocks {CLOCK_50}] -rise_to [get_clocks {CLOCK_50}] 0.020 set_clock_uncertainty -fall_from [get_clocks {CLOCK_50}] -fall_to [get_clocks {CLOCK_50}] 0.020 derive_pll_clocks derive_clock_uncertainty Here is a screen shot of my Clock Status Summary from Quartus: https://alteraforum.com/forum/attachment.php?attachmentid=13866&stc=1
