Max10 RSU post config status

So I'm looking at the Dual Config Core registers at offset 5 and 6 which are defined as follow from the data sheet:

Specifically, I'm looking the Bit 3:0 in each register which defines what caused a reconfiguration of the device. If I understand correctly this would tell me in the event of some failure what caused it. The definition of these bits I'm taking from another part of the data sheet:

This is where the datasheet is confusing. As it seems the above table 13 is showing a status register from some internal logic in the device. Here I presumed that bits [31:28] which describe reconfiguration sources, are the same reconfiguration sources as in the Dual Config Core, just mapped into offsets 0x5 and 0x6 (bits [3:0] of the core avalon bus status registers.

I had presumed that these should all be 0 in the event of a successful RSU, which they indeed are when I cold boot the device. But on a warm boot, right after configuration, I seem to sometimes get a non-zero value on one or more of the 4 config sources (nconfig,crc error, nstatus, wdtimer), this is what I mean by erroneous status. But even here the device loaded successfully, so it looks like only a status reporting problem on a warm boot.