Forum Discussion
15 Replies
- Altera_Forum
Honored Contributor
Hi Alan Ismail,
I'm very interested in your website explaining how to upgrade the MAX10 FPGA over EtherCAT. Is there any Open Source sharing VHDL or Verilog about this part? I did't found on the website.(https://embeddedfpgadesign.wordpress.com) I'm also using EtherCAT but try to implement this solution without FPGA1 intermadiate. Please can you help me ASAP? Thanks, - Altera_Forum
Honored Contributor
There are some reference designs in Altera/Intel reaources that you can download. Updating via EtherCAT is not much difference to other protocol, as long as you have proper EtherCAT slave stack implemented on your microp you will get the data in ET mailbox. From there it is just a matter of writing a small controller to control the Erase & Write of CFM flash. You can pm me & I'll be glad to give additional pointers
- Altera_Forum
Honored Contributor
Ok Thank you I'll see it.
- Altera_Forum
Honored Contributor
@AlanIsmail
In the original NIOS based design, I see some bit manipulating before writing to the flash (get_word_bitswap). Do you do these manipulations at the MCU side? Thanks. - Altera_Forum
Honored Contributor
--- Quote Start --- @AlanIsmail In the original NIOS based design, I see some bit manipulating before writing to the flash (get_word_bitswap). Do you do these manipulations at the MCU side? Thanks. --- Quote End --- The word_bitswap can be done in MCU or FPGA. I believe the swap is to ensure data format matches the Flash native data format