Honored Contributor
Honored ContributorI have recently completed a prototype to update Max10 CFM1&2 over EtherCAT ( similar to Ethernet) in realtime. I agree, this is not a simple exercise. My hardware configuration is slightly different where I have another FPGA sits between the CPU to Max10 device.
EtherCAT --> DSP --> FPGA1 ---> Max10. The I2CRSU is a great start but it requires quite significant modification as my interface from FPGA1 to Max10 is SPI. In addition to that, the real time requirement and makes the processor controlled CFM programming not practical, thus requiring separate RSU master to control the flash erase and reprogramming Sifting through tons of Altera information is not an easy feat as well and I found that Altera has not been consistent in their image definition. Sometimes called image 1 and 2 and other intances image 0 and 1. I am trying to put a blog (https://embeddedfpgadesign.wordpress.com/) on the changes that I made to make this happen. Hopefully others may benefit from it. You can contact me if you need more details.
