Forum Discussion
Altera_Forum
Honored Contributor
10 years agoThis is not looking good.
This is a replacement design for existing product. Previous design used Xilinx spartan fpga which was loaded through an I/O bit-banging interface from an MCU at power up. The MCU connected to the outside world with ethernet, therefore it was possible to update the MCU with the fpga configuration file, and the MCU would handle the configuration file update to the fpga. The new design task is to replace this now obsolete fpga with the Altera Max 10, and still have it re-configurable in the field in the same manner -ethernet to MCU to fpga. As I'm on the software side of this thing, I started looking into 'how the max 10 may be updated from an mcu'. Yikes. Making matters a bit worse, if that's possible, I seriously anticipate the new design will not be getting much of a validation test, as the system is well beyond the commissioning phase, so I strongly believe the need for field updates is real. Alex, if I understand correctly, the SVF format requires a JTAG programmer. I've seen the reference to serial updates over a UART, etc., but nothing as I've described the need for, as you point out. Really appreciate any further thoughts you have on this, as it appears we're going down a dangerous slope. Thanks, Bob