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rt52's avatar
rt52
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

MAX10 Read Dual Boot IP core values in simulation

I can successfully perform an RSU using discrete logic implementation on a MAX10 device. I now want to confirm that the correct image has been loaded. My board has the CONFIG_SEL pin pulled up so i...
YuanLi_S_Intel's avatar
YuanLi_S_Intel
Icon for Regular Contributor rankRegular Contributor
5 years ago

Are you saying that you were using 3'h1 in Quartus Design and now changed to 3'b001 and it works now?


rt52's avatar
rt52
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

That was the last HDL change I made before it worked. I also added signal tap to look at the registers and saw it go from not working to working in signal tap. I made no other logic/state machine changes and it still does not work in simulation