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Altera_Forum
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11 years ago

max10 on chip flash read/write in nios

hi everone, for two weeks i stuck in the max10 on chip flash read/write in nios.

in my project, it has a nios system and the clk frequency is 100mHz.

i want to use the internal configuration mode of max10(single compressed image with memory initialization), as well as read/write the chip flash UFM in nios.

i can read the UFM, but i can not write to it.

the following is my code, i run it in debug mode

flash_status_reg1=IORD_32DIRECT(ONCHIP_FLASH_0_CSR_BASE,0x0); // read the flash_status_reg, the result is 0xfffffc04,

flash_control_reg1=IORD_32DIRECT(ONCHIP_FLASH_0_CSR_BASE,0x4); // read the flash_control_reg, the result is 0x3fffffff,

flash_data_reg1=IORD_32DIRECT(ONCHIP_FLASH_0_DATA_BASE,0x0); // read the first 32 bit of UFM1,the result is 0x0,

while(1)

{

flash_status_reg1=IORD_32DIRECT(ONCHIP_FLASH_0_CSR_BASE,0x0);//read the flash_status_reg, the result is 0xfffffc04, it means read success

flash_status_reg1=flash_status_reg1&0x4;

if (flash_status_reg1== 0x4) break; // write success

}

// write to UFM1

IOWR_32DIRECT(ONCHIP_FLASH_0_CSR_BASE,0x4,0xff7fffff);// disable the write protection of UFM1

flash_control_reg1=IORD_32DIRECT(ONCHIP_FLASH_0_CSR_BASE,0x4);// read the flash_control_reg, the result is 0x3f7fffff,

IOWR_32DIRECT(ONCHIP_FLASH_0_DATA_BASE,0x0,0x12345678);// write to the first 32 bit of UFM1, then the debug stuck in here

can someone gives me some help?

i have found the reference desin for how to use the UFM in quartus without nios;

i also have found the reference desin for how to use the onchip internal configuration mode of max10 in nios system;

but i have not found a reference desin use nios, and the UFM

thanks!

11 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    Hi,

    Have you try to erase before write? Typical CPLD and flash require erase operation before write. Thus you need to disable write protect and erase first before write to UFM1. Try setting CSR to 0x001fffff or 0xff1fffff to disable write protect and erase for UFM1.