Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

max10 on chip flash read/write in nios

hi everone, for two weeks i stuck in the max10 on chip flash read/write in nios. in my project, it has a nios system and the clk frequency is 100mHz. i want to use the internal configuration mod...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

I'm don't have any design with Nios as I'm not that familiar on Nios.

I heard that Altera is going to publish a reference design on accessing the CFM and UFM with Nios using the on chip flash and dual boot ip.

Yes, in CPLD (MAX II and MAX V too) you need to erase before write. Somewhere in the MAX 10 handbook should have stated on this.

Also, you need to set the write protect once complete write. This is stated from the UFM user guide.