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Hello,
Thank you for your answer.
However, the table refers to VCCIO pin(s). These pins are correctly fed with 3,3V in our design.
The concern is only about the VCCA# pins.
Or did I misinterpret something?
Hello,
I believe you are referring to the same thing. Please refer to page 30 of the same document for more information about VCCIO Range Considerations.
Thanks
- MathiasB4 years ago
Occasional Contributor
Hello,
My understanding is that VCCIO pins are the ones powering the CPLD's IO banks, while the VCCA pins are dedicated to PLL analog block.
I got this from https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/dp/max-10/pcg-01018.pdf page 16 and https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/max-10/m10_datasheet.pdf page 7.
The latter also mentions the absolute maximum ratings I mentioned in my first message on pages 4&5.
Thanks
- AminT_Intel4 years ago
Regular Contributor
Hello,
Sorry for the confusion. Yes you are correct. As stated in the document, conditions outside the range listed in the absolute maximum ratings tables may cause permanent damage to the device. Device operation at the absolute maximum ratings for extended periods of time may have adverse effects on the device.
Thank you
- AminT_Intel4 years ago
Regular Contributor
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