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_MZ_'s avatar
_MZ_
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4 years ago

MAX10 GPIO Lite DDR Input Error

Salam I am working on MAX10M25SCE144I7G FPGA and instantiate a DDR input at pin 46 using the IP Catalog Wizard. But the fitter gives the following error: "Error (171000): Can't fit design in...
_MZ_'s avatar
_MZ_
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4 years ago

Thanks for your reply.

I have read all possible related documents but haven't find any information that DDR input is not supported at this specific pin. Interestingly other pins around this pin i can use as DDR inputs but this specific pin not. So as a last resort i have ended up on this forum for any precise clue/information.

AminT_Intel's avatar
AminT_Intel
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4 years ago

Hello,

Have you checked other specs as well? The device IO standards, range of voltage, etc? That could give the same error as well

Thank you

  • AminT_Intel's avatar
    AminT_Intel
    Icon for Regular Contributor rankRegular Contributor
    4 years ago

    We do not receive any response from you to the previous question/reply/answer that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.

  • _MZ_'s avatar
    _MZ_
    Icon for New Contributor rankNew Contributor
    4 years ago

    Yes everything checked. Pin 46 is is present in Bank 3 and all the banks are provided with 3.3V and in the Pin Planner it is set to 3.3-V LVCMOS. This input is interfaced with a chip and receives data.