Honored ContributorHello Community,
im trying to get the ADC on the MAX10 running with a samplerate lower than 1 MSPS. According to the Datasheet the ADC schould run at a maximum of 1 MSPS. The ADC runs fine with 1 MSPS but if i lower the Inputclock of the ADC the ADC stops operation. Has anyone get the ADC running at a samplerate lower than 1 MSPS? With kind regards, m4pp3t
Honored Contributorhi
i guess the sample rate is fixed in max 10 onchip adc, but it is possible to make the sample rate lower method 1: maybe you can write hdl to control the adc, enable it =>get the result=>disable it =>wait 1us =>enable it =>get the result..... method 2: there are many channels for the max 10 adc, you can enable several channels to reduce the sample rate, for example, if the sample rate you want is 0.5MSPs, the analoge signal is in channel 0 then you can enable both channel 0 and channel 1 , then make the sequencer slot 1 => CH0 slot 2 => CH1 the alter has a reference design for how to use the max10 adc in quartus by verilog (not in nios system) https://cloud.altera.com/devstore/platform/?acds_version=14.1.0 ADC and Audio Monitor hope my advise helpful! if it really helps, please let me know!Honored Contributoryou can get a lower sampling rate by following below kdb:
https://www.altera.com/support/support-resources/knowledge-base/solutions/rd04292015_222.html basically what you are doing is to trick the ADC by providing 10Mhz, but setting it with 20Mhz.Honored ContributorI think the 20MHz setting appear is set the reference clock in for the ADC IP...nice "cheat"....
